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? semiconductor components industries, llc, 2014 august, 2014 ? rev. 15 1 publication order number: mc74hc4538a/d mc74hc4538a dual precision monostable multivibrator (retriggerable, resettable) the mc74hc4538a is identical in pinout to the mc14538b. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. this dual monostable multivibrator may be triggered by either the positive or the negative edge of an input pulse, and produces a precision output pulse over a wide range of pulse widths. because the device has conditioned trigger inputs, there are no trigger?input rise and fall time restrictions. the output pulse width is determined by the external timing components, r x and c x . the device has a reset function which forces the q output low and the q output high, regardless of the state of the output pulse circuitry. features ? unlimited rise and fall times allowed on the trigger inputs ? output pulse is independent of the trigger pulse width ? 10% guaranteed pulse width variation from part to part (using the same test jig) ? output drive capability: 10 lsttl loads ? outputs directly interface to cmos, nmos and ttl ? operating voltage range: 3.0 to 6.0 v ? low input current: 1.0 a ? high noise immunity characteristic of cmos devices ? in compliance with the requirements defined by jedec standard no. 7 a ? chip complexity: 145 fets or 36 equivalent gates ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free, halogen free and are rohs compliant http://onsemi.com marking diagrams soic?16 d suffix case 751b tssop?16 dt suffix case 948f 1 16 hc4538ag awlyww hc45 38a alyw 1 16 see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information a = assembly location l, wl = wafer lot y, yy = year w, ww = work week g or = pb?free package (note: microdot may be in either location) soic?16 tssop?16 pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 a2 reset 2 c x 2/r x 2 gnd v cc q2 q2 b2 a1 reset 1 c x 1/r x 1 gnd gnd q1 q1 b1
mc74hc4538a http://onsemi.com 2 figure 1. logic diagram pin 16 = v cc pin 8 = gnd r x and c x are external components pin 1 and pin 15 must be hard wired to gnd c x 1r x 1 v cc q1 reset 1 b1 a1 trigger inputs q1 12 4 5 3 6 7 c x 2r x 2 v cc q2 reset 2 b2 a2 trigger inputs q2 15 14 12 11 13 10 9 function table inputs outputs reset a b q q hh hl h x l not triggered h h x not triggered h l,h, h not triggered h l l,h, not triggered lx x lh x x not triggered ordering information device package shipping ? mc74hc4538adg soic?16 (pb?free) 48 units / rail mc74hc4538adr2g soic?16 (pb?free) 2500 / tape & reel nlv74hc4538adr2g* soic?16 (pb?free) 2500 / tape & reel mc74hc4538adtr2g tssop?16 (pb?free) 2500 / tape & reel NLVHC4538ADTR2G* tssop?16 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable
mc74hc4538a http://onsemi.com 3 maximum ratings symbol parameter value unit v cc dc supply voltage ?0.5 to +7.0 v v i dc input voltage ?0.5 v i v cc + 0.5 v v o dc output voltage (note 1) ?0.5 v o v cc + 0.5 v i ik dc input diode current a, b, reset c x , r x 20 30 ma i ok dc output diode current 25 ma i o dc output sink current 25 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per ground pin 100 ma t stg storage temperature range ?65 to +150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias +150 c ja thermal resistance soic tssop 112 148 c/w p d power dissipation in still air at 85 c soic tssop 500 450 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% ? 35% ul?94?vo (0.125 in) v esd esd withstand voltage human body model (note 2) machine model (note 3) charged device model (note 4) > 2000 > 100 > 500 v i latchup latchup performance above v cc and below gnd at 85 c (note 5) 300 ma stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. i o absolute maximum rating must be observed. 2. tested to eia/jesd22?a114?a. 3. tested to eia/jesd22?a115?a. 4. tested to jesd22?c101?a. 5. tested to eia/jesd78. recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ?55 +125 c t r , t f input rise and fall time v cc = 2.0 v (figure 6) v cc = 4.5 v v cc = 6.0 v a or b (figure 4) 0 0 0 ? 1000 500 400 no limit ns r x external timing resistor v cc < 4.5 v v cc 4.5 v 1.0 2.0 ? ? k c x external timing capacitor 0 ? f functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. ?the maximum allowable values of r x and c x are a function of the leakage of capacitor c x , the leakage of the hc4538a, and leakage due to board layout and surface resistance. for most applications, c x /r x should be limited to a maximum value of 10 f/1.0 m . values of c x >1.0 f may cause a problem during power down (see power down considerations). susceptibility to externally induced noise signals may occur for r x >1.0m . 6. unused inputs may not be left open. all inputs must be tied to a high?logic voltage level or a low?logic input voltage level.
mc74hc4538a http://onsemi.com 4 dc characteristics symbo l parameter test conditions v cc v guaranteed limits unit ?55 to 25 c 85 c 125 c min typ max min typ max min typ max v ih minimum high?level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 v v il maximum low?level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 v v oh minimum high?level output voltage v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in = v ih or v il |i out | ? 4.0 ma |i out | ? 5.2 ma 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 v ol maximum low?level output voltage v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il |i out | 4.0 ma |i out | 5.2 ma 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 i in maximum input leakage current (a, b, reset) v in = v cc or gnd 6.0 0.1 1.0 1.0 a i in maximum input leakage current (r x , c x ) v in = v cc or gnd 6.0 50 500 500 na i cc maximum quiescent supply current (per package) standby state v in = v cc or gnd q1 and q2 = low i out = 0 a 6.0 130 220 350 a i cc maximum supply current (per package) active state v in = v cc or gnd q1 and q2 = high i out = 0 a pins 2 and 14 = 0.5 v cc 6.0 25 c ?45 c to 85 c ?55 c to 125 c a 400 600 800 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
mc74hc4538a http://onsemi.com 5 ac characteristics (c l = 50 pf, input t r = t f = 6.0 ns) symbo l parameter v cc v guaranteed limits unit ?55 to 25 c 85 c 125 c min max min max min max t plh maximum propagation delay input a or b to q (figures 5 and 7) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns t phl maximum propagation delay input a or b to nq (figures 5 and 7) 2.0 4.5 6.0 195 39 33 245 49 42 295 59 50 ns t phl maximum propagation delay reset to q (figures 6 and 7) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns t plh maximum propagation delay reset to nq (figures 6 and 7) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns t tlh, t thl maximum output transition time, any output (figures 6 and 7) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns c in maximum input capacitance (a. b, reset) (c x , r x ) ? 10 25 10 25 10 25 pf c pd power dissipation capacitance (per multivibrator)* typical @ 25 c, v cc = 5.0 v pf 150 *used to determine the no?load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . timing characteristics (input t r = t f = 6.0 ns) symbo l parameter v cc v guaranteed limits unit ?55 to 25 c 85 c 125 c min max min max min max t rr minimum retrigger time, input a or b (figure 6) (note 7) 2.0 4.5 6.0 ? ? ? ? ? ? ns t rec minimum recovery time, inactive to a or b (figure 6) 2.0 4.5 6.0 0 0 0 0 0 0 0 0 0 ns t w minimum pulse width, input a or b (figure 5) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns t w minimum pulse width, reset (figure 6) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns t r , t f maximum input rise and fall times, reset (figure 6) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns a or b (figure 6) 2.0 4.5 6.0 no limit 7. t rr (ns) v cc (volts) c x (pf) 30.5
mc74hc4538a http://onsemi.com 6 output pulse width characteristics (r x = 10 k , c x = 0.1 f, c l = 50 pf) symbo l parameter conditions guaranteed limits unit timing components v cc v ?55 to 25 c 85 c 125 c min max min max min max output pulse width (note 8) (figures 5 and 6) r x = 10 k , c x = 0.1 f 5.0 0.63 0.77 0.6 0.8 0.59 0.81 ms pulse width match between circuits in the same package 5.0 % pulse width match variation (part to part) (note 10) 10 % output pulse width characteristics (r x = 100 k , c x = 1 nf, c l = 50 pf) symbo l parameter conditions guaranteed limits unit timing components v cc v ambient temperature min typ max output pulse width (note 9) r x = 100 k , c x = 1 nf 5.0 25 c ? 79 ? s pulse width match between circuits in the same package ?55 to 125 c ?5.0 ? +5.0 % pulse width match variation (part to part) (note 10) ?55 to 125 c ?10 ? +10 % ? temperature variance ?55 to 125 c ? +0.05 ? s/ c ? power supply variance ?55 to 125 c ? ?8.0 ? s/v 8. = kr x c x and k = 0.7 for the output pulse width corresponding to r x = 10 k , c x = 0.1 f. 9. = kr x c x and k = 0.79 for the output pulse width corresponding to r x = 100 k , c x = 1 nf. 10. pulse width match variation between ics (part?to?part) is defined with identical r x , c x , v cc and a specific temperature.
mc74hc4538a http://onsemi.com 7 typical characteristics figure 2. typical output pulse width constant, k, versus supply voltage (for output pulse widths > 100 s: = kr x c x ) figure 3. output pulse width versus timing capacitance figure 4. normalized output pulse width versus power supply voltage 0.70 0.60 0.50 0.65 0.55 10 s 1 s 100 ms 10 ms 1 ms 100 s 10 s 1 s 100 ns 1.30 1.20 1.10 1.00 0.90 0.80 1234567 0.00001 0.0001 0.001 0.01 0.1 1 10 1234567 v cc , power supply voltage (volts) capacitance ( f) v cc , power supply voltage (volts) (normalized to 5 v number) t a = 25 c v cc = 5 v, t a = 25 c t a = 25 c r x = 100 k c x = 1000 pf r x = 1 m c x = 0.1 f 1 k 10 k 1 m 100 k k, output pulse width constant (typical) output pulse width ( ) output pulse width ( ) figure 5. normalized output pulse width versus power supply voltage 1.075 1.05 1.025 1.0 0.975 0.95 ?75 ?50 ?25 0 25 50 75 100 125 150 t a , ambient temperature ( c) v cc = 6 v v cc = 3 v output pulse width ( ) (normalized to 25 c number) figure 6. normalized output pulse width versus power supply voltage 1.025 1.02 1.015 1.01 1.005 1.00 25 50 75 100 12 5 t a , ambient temperature ( c) v cc = 5.5 v v cc = 4.5 v v cc = 5 v output pulse width ( ) (normalized to 25 c number)
mc74hc4538a http://onsemi.com 8 a b q q 50% t plh 50% 50% t plh 50% gnd v cc gnd v cc t w(h) t w(l) t phl t phl figure 7. switching waveform a b reset q q t r t f 90% 10% t f t tlh t thl 90% 10% 90% 10% t plh t phl 50% 50% t f 90% 10% 50% 50% (retriggered pulse) 50% gnd v cc gnd v cc gnd v cc t w(l) t rec + t rr t rr figure 8. switching waveform *includes all probe and jig capacitance figure 9. test circuit c l * test point device under test output
mc74hc4538a http://onsemi.com 9 pin descriptions inputs a1, a2 (pins 4, 12) positive?edge trigger inputs. a rising?edge signal on either of these pins triggers the corresponding multivibrator when there is a high level on the b1 or b2 input. b1, b2 (pins 5, 11) negative?edge trigger inputs. a falling?edge signal on either of these pins triggers the corresponding multivibrator when there is a low level on the a1 or a2 input. reset 1, reset 2 (pins 3, 13) reset inputs (active low). when a low level is applied to one of these pins, the q output of the corresponding multivibrator is reset to a low level and the q output is set to a high level. c x 1/r x 1 and c x 2/r x 2 (pins 2 and 14) external timing components. these pins are tied to the common points of the external timing resistors and capacitors ( see the block diagram). polystyrene capacitors are recommended for optimum pulse width control. electrolytic capacitors are not recommended due to high leakages associated with these type capacitors. gnd (pins 1 and 15) external ground. the external timing capacitors discharge to ground through these pins. outputs q1, q2 (pins 6, 10) noninverted monostable outputs. these pins (normally low) pulse high when the multivibrator is triggered at either the a or the b input. the width of the pulse is determined by the external timing components, r x and c x . q1 , q2 (pins 7, 9) inverted monostable outputs. these pins (normally high) pulse low when the multivibrator is triggered at eit her the a or the b input. these outputs are the inverse of q1 and q2. + ? + ? rxcx v cc m1 2 k m3 m2 a b reset power on reset reset latch trigger control reset circuit trigger control circuit output latch upper reference circuit v re , upper lower reference circuit v re , lower q q c cb q r v cc figure 10. logic detail (1/2 the device)
mc74hc4538a http://onsemi.com 10 circuit operation figure 11 shows the hc4538a configured in the retriggerable mode. briefly, the device operates as follows (refer to figure 10): in the quiescent state, the external timing capacitor, c x , is charged to v cc . when a trigger occurs, the q output goes high and c x discharges quickly to the lower reference voltage (v ref lower 1/3 v cc ). c x then charges, through r x , back up to the upper reference voltage (v ref upper 2/3 v cc ), at which point the one?shot has timed out and the q output goes low. the following, more detailed description of the circuit operation refers to both the logic detail (figure 10) and the timing diagram (figure 11). quiescent state in the quiescent state, before an input trigger appears, the output latch is high and the reset latch is high (#1 in figure 11). thus the q output (pin 6 or 10) of the monostable multivibrator is low (#2, figure 11). the output of the trigger?control circuit is low (#3), and transistors m1, m2, and m3 are turned off. the external timing capacitor, c x , is charged to v cc (#4), and both the upper and lower reference circuit has a low output (#5). in addition, the output of the trigger?control reset circuit is low. trigger operation the hc4538a is triggered by either a rising?edge signal at input a (#7) or a falling?edge signal at input b (#8), with the unused trigger input and the reset input held at the voltage levels shown in the function table. either trigger signal will cause the output of the trigger?control circuit to go high (#9). the trigger?control circuit going high simultaneously initiates two events. first, the output latch goes low, thus taking the q output of the hc4538a to a high state (#10). second, transistor m3 is turned on, which allows the external timing capacitor, c x , to rapidly discharge toward ground (#1 1). (note that the voltage across c x appears at the input of both the upper and lower reference circuit comparator). when c x discharges to the reference voltage of the lower reference circuit (#12), the outputs of both reference circuits will be high (#13). the trigger?control reset circuit goes high, resetting the trigger?control circuit flip?flop to a low state (#14). this turns transistor m3 off again, allowing c x to begin to charge back up toward v cc , with a time constant t = r x c x (#15). once the voltage across c x charges to above the lower reference voltage, the lower re ference circuit will go low allowing the monostable multivibrator to be retriggered. 2 18 1 6 5 4 17 14 3 9 8 quiescent state trigger cycle (a input) trigger cycle (b input) reset retrigger t rr v ref upper v ref lower trigger input a (pin 4 or 12) trigger input b (pin 5 or 11) trigger-control circuit output r x /c x input (pin 2 or 14) upper reference circuit reset input (pin 3 or 13) reset latch q output (pin 6 or 10) figure 11. timing diagram 10 11 12 13 15 16 19 20 21 22 23 24 25 + t rr 13 7 lower reference circuit
mc74hc4538a http://onsemi.com 11 when c x charges up to the reference voltage of the upper reference circuit (#17), the output of the upper reference circuit goes low (#18). this causes the output latch to toggle, taking the q output of the hc4538a to a low state (#19), and completing the time?out cycle. power?down considerations large values of c x may cause problems when powering down the hc4538a because of the amount of energy stored in the capacitor. when a system containing this device is powered down, the capacitor may discharge from v cc through the input protection diodes at pin 2 or pin 14. current through the protection diodes must be limited to 30 ma; therefore, the turn?off time of the v cc power supply must not be faster than t = v cc c x /(30 ma). for example, if v cc = 5.0 v and c x = 15 f, the v cc supply must turn off no faster than t = (5.0 v) (15 f)/30 ma = 2.5 ms. this is usually not a problem because power supplies are heavily filtered and cannot discharge at this rate. when a more rapid decrease of v cc to zero volts occurs, the hc4538a may sustai n damage. to avoid this possibility, use an external damping diode, d x , connected as shown in figure 12. best results can be achieved if diode d x is chosen to be a germanium or schottky type diode able to withstand large current surges. reset and power on reset operation a low voltage applied to the reset pin always forces the q output of the hc4538a to a low state. the timing diagram illustrates the case in which reset occurs (#20) while c x is charging up toward the reference voltage of the upper reference circuit (#21). when a reset occurs, the output of the reset latch goes low (#22), turning on transistor m1. thus c x is allowed to quickly charge up to v cc (#23) to await the next trigger signal. on power up of the hc4538a the power?on reset circuit will be high causing a reset condition. this will prevent the trigger?control circuit from accepting a trigger input during this state. the hc4538a?s q outputs are low and the q not outputs are high. retrigger operation when used in the retriggerable mode (figure 13), the hc4538a may be retriggered during timing out of the output pulse at any time after the trigger?control circuit flip?flop has been reset (#24), and the voltage across c x is above the lower reference voltage. as long as the c x voltage is below the lower reference voltage, the reset of the flip?flop is high, disabling any trigger pulse. this prevents m3 from turning on during this period resulting in an output pulse width that is predictable. the amount of undershoot voltage on r x c x during the trigger mode is a function of loop delay, m3 conductivity, and v dd . minimum retrigger time, trr (figure 7), is a function of 1) time to discharge r x c x from v dd to lower reference voltage (t discharge ); 2) loop delay (t delay ); 3) time to charge r x c x from the undershoot voltage back to the lower reference voltage (t charge ). figure 14 shows the device configured in the non?retriggerable mode. for additional information, please see application note (an1558/d) titled characterization of retrigger time in the hc4538a dual precision monostable multivibrator . d x c x v cc q q reset a b figure 12. discharge protection during power down r x
mc74hc4538a http://onsemi.com 12 typical applications reset = v cc b = v cc reset = v cc rising?edge trigger a = gnd reset = v cc reset = v cc falling?edge trigger figure 13. retriggerable monostable circuitry figure 14. non?retriggerable monostable circuitry c x v cc q q a b r x c x v cc q q a b r x c x v cc q q b r x c x v cc q q a b r x figure 15. connection of unused section a = gnd reset r x c x v cc q q b gnd n/c n/c n/c rising?edge trigger falling?edge trigger one?shot selection guide 100 ns 1 s10 s 100 s 1ms 10ms 100ms 1s 10s mc14528b mc14536b mc14538b mc14541b hc4538a* *limited operating voltage (2 ?6 v) 23 hr 5 min total output pulse width range recommended pulse width range
mc74hc4538a http://onsemi.com 13 package dimensions tssop?16 case 948f issue b ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. section n?n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74hc4538a http://onsemi.com 14 package dimensions soic?16 case 751b?05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 8x *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc74hc4538a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.

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